New CMOS VLSI Linear Self-Timed Architectures

摘要

The implementation of digital signal processor circuitsvia self-timed techniques is currently a valid altemativeto solve some problems encountered in synchronousVLSI circuits. However; a main difference between synchronousand asynchronous circuits is the hardware resourcesneeded to implement asynchronous circuits. Thiscommunication presents four less-costly alternatives to apreviously reported linear selftimed architecture, andtheir application in the design of FIFO memories. Furthermore,the integration and characterization in the laboratoryof prototypes of these FIFOs are presented.